A mechanical stress is applied to a bonding pad formed on a semiconductor chip upper surface in the case of probing in an electrical test of a semiconductor chip, and a wire bonding at the time of assembly of a semiconductor device. The stress applied to the bonding pad makes the interlayer insulation film under the pad concerned generate a crack, and has become a cause which causes a pad separation at the time of wire bonding.
Therefore, a method of making the metal layer concerned absorb the stress was conventionally taken by laying a metal layer, such as tungsten, as a foundation of the bonding pad. Usually, a bonding pad is formed using an uppermost wiring layer (top layer wiring layer), and a metal layer of the foundation is formed using a via hole (Via) for connecting an upper wiring layer and the wiring layer under it (lower-layer wiring layer). That is, formation of a foundation metal layer is performed at the same step as the original formation of a via hole for connecting an upper wiring layer and a lower-layer wiring layer.
It is necessary to make the size of a foundation metal layer into same extent as the size of a bonding pad, and it becomes a large caliber extremely as compared with an original via hole. Therefore, in the manufacturing process of a conventional semiconductor device, a via hole (foundation metal layer) of a large caliber and a via hole (original via hole) of a small caliber are formed simultaneously. However, since a via hole of a large caliber differs in an etch rate from a via hole of a small caliber, it is difficult to obtain suitable etching quantity in both the via hole of the large caliber, and the via hole of the small caliber, and the forming accuracy will fall. When making a metal deposit in a via hole, since a via hole of a large caliber takes a long time to bury a metal thoroughly compared with that of a small caliber, the thickness of the metal cannot be fully secured, but it is easy to cause dishing of the upper surface of the via hole of the large caliber, originating from it. That is, since the height of the upper surface of the foundation metal layer becomes uneven, it will become difficult to make uniform the height of the upper surface of the bonding pad formed on it. Sure probing and wire bonding will become difficult when the height of the upper surface of the bonding pad is uneven, and the reliability of the semiconductor device will fall.
On the other hand, the technology which makes a foundation metal layer of a bonding pad a shape of a plurality of lines (shape of a long size) instead of a via hole of a large caliber, and forms it is known (for example, Patent References 1-3). The upper problem will be solved when a foundation metal layer is made into a shape of a plurality of lines.    [Patent Reference 1] Japanese Unexamined Patent Publication No. 2002-110731    [Patent Reference 2] Japanese Unexamined Patent Publication No. Hei 10-199925    [Patent Reference 3] Japanese Unexamined Patent Publication No. Hei 6-196525
However, when a foundation metal layer of a bonding pad is made into a shape of a plurality of lines and formed, as compared with the case where a via hole of a large caliber is formed as a foundation metal layer, we are anxious about strength falling greatly to the stress from a specific direction. In Patent Reference 1, for example, it is disclosed that when a long-side direction of a foundation metal layer (the direction of a line) and an advancement direction of a probe in the case of probing become vertical in plan view (namely, when an applying direction of a stress is vertical to a direction of a line of a foundation metal layer in plan view), it is easy to generate a crack from between the side wall of a line-like foundation metal layer and the interlayer film.
When a crack occurs in an insulating layer under a bonding pad and it reaches even a wiring according to the stress from the outside applied to the bonding pad, the metal migration resistance of the wiring concerned will deteriorate. The structure located so that wirings may pass along a lower part of a bonding pad is in the tendency that the strength is comparatively weak and a crack becomes easy to generate. Therefore, in order to prevent the generation of a crack, it is desirable not to let wirings pass carelessly in the lower part of the bonding pad. However, in order to integrate a semiconductor device highly, the region under a bonding pad is also needed to be used effectively and it is obliged to locate wirings also under the bonding pad.